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Track simulator fidelity experiment artifacts

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Gahow Wang
2026-07-19 15:31:09 +08:00
parent e0ea7e9961
commit 4c8d581a5b
115 changed files with 42355 additions and 0 deletions
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runs/frontier-multicase-sufficiency-v1/results/t0-final/capacity.csv Normal file
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slo,config,tp,mns,mbt,real_capacity_per_gpu,sim_capacity_per_gpu,real_boundary_status,expansion_required
tpot_40ms,tp4_mns64_mbt8192,4,64,8192,,,lowest_anchor_infeasible,False
tpot_40ms,tp4_mns64_mbt16384,4,64,16384,,,lowest_anchor_infeasible,False
tpot_40ms,tp4_mns128_mbt8192,4,128,8192,,,lowest_anchor_infeasible,False
tpot_40ms,tp4_mns128_mbt16384,4,128,16384,,,lowest_anchor_infeasible,False
tpot_40ms,tp8_mns64_mbt8192,8,64,8192,,,lowest_anchor_infeasible,False
tpot_40ms,tp8_mns64_mbt16384,8,64,16384,,,lowest_anchor_infeasible,False
tpot_40ms,tp8_mns128_mbt8192,8,128,8192,,,lowest_anchor_infeasible,False
tpot_40ms,tp8_mns128_mbt16384,8,128,16384,,,lowest_anchor_infeasible,False
tpot_120ms,tp4_mns64_mbt8192,4,64,8192,0.025,0.2,unbracketed_requires_expansion,True
tpot_120ms,tp4_mns64_mbt16384,4,64,16384,0.025,0.2,unbracketed_requires_expansion,True
tpot_120ms,tp4_mns128_mbt8192,4,128,8192,0.025,0.2,unbracketed_requires_expansion,True
tpot_120ms,tp4_mns128_mbt16384,4,128,16384,0.025,0.2,unbracketed_requires_expansion,True
tpot_120ms,tp8_mns64_mbt8192,8,64,8192,0.0125,0.05,unbracketed_requires_expansion,True
tpot_120ms,tp8_mns64_mbt16384,8,64,16384,0.0125,0.05,unbracketed_requires_expansion,True
tpot_120ms,tp8_mns128_mbt8192,8,128,8192,0.0125,0.05,unbracketed_requires_expansion,True
tpot_120ms,tp8_mns128_mbt16384,8,128,16384,0.0125,0.05,unbracketed_requires_expansion,True
tpot_150ms,tp4_mns64_mbt8192,4,64,8192,0.6,0.4,adjacent_transition_bracketed,False
tpot_150ms,tp4_mns64_mbt16384,4,64,16384,0.6,0.4,adjacent_transition_bracketed,False
tpot_150ms,tp4_mns128_mbt8192,4,128,8192,0.6,0.4,adjacent_transition_bracketed,False
tpot_150ms,tp4_mns128_mbt16384,4,128,16384,0.6,0.4,adjacent_transition_bracketed,False
tpot_150ms,tp8_mns64_mbt8192,8,64,8192,0.3,0.15,adjacent_transition_bracketed,False
tpot_150ms,tp8_mns64_mbt16384,8,64,16384,0.2,0.15,adjacent_transition_bracketed,False
tpot_150ms,tp8_mns128_mbt8192,8,128,8192,0.2,0.15,adjacent_transition_bracketed,False
tpot_150ms,tp8_mns128_mbt16384,8,128,16384,0.3,0.15,adjacent_transition_bracketed,False
tpot_180ms,tp4_mns64_mbt8192,4,64,8192,0.8,0.6,upper_lattice_reached,False
tpot_180ms,tp4_mns64_mbt16384,4,64,16384,0.8,0.6,upper_lattice_reached,False
tpot_180ms,tp4_mns128_mbt8192,4,128,8192,0.8,0.6,upper_lattice_reached,False
tpot_180ms,tp4_mns128_mbt16384,4,128,16384,0.8,0.6,upper_lattice_reached,False
tpot_180ms,tp8_mns64_mbt8192,8,64,8192,0.4,0.2,upper_lattice_reached,False
tpot_180ms,tp8_mns64_mbt16384,8,64,16384,0.3,0.2,unbracketed_requires_expansion,True
tpot_180ms,tp8_mns128_mbt8192,8,128,8192,0.3,0.2,unbracketed_requires_expansion,True
tpot_180ms,tp8_mns128_mbt16384,8,128,16384,0.4,0.2,upper_lattice_reached,False
1 slo config tp mns mbt real_capacity_per_gpu sim_capacity_per_gpu real_boundary_status expansion_required
2 tpot_40ms tp4_mns64_mbt8192 4 64 8192 lowest_anchor_infeasible False
3 tpot_40ms tp4_mns64_mbt16384 4 64 16384 lowest_anchor_infeasible False
4 tpot_40ms tp4_mns128_mbt8192 4 128 8192 lowest_anchor_infeasible False
5 tpot_40ms tp4_mns128_mbt16384 4 128 16384 lowest_anchor_infeasible False
6 tpot_40ms tp8_mns64_mbt8192 8 64 8192 lowest_anchor_infeasible False
7 tpot_40ms tp8_mns64_mbt16384 8 64 16384 lowest_anchor_infeasible False
8 tpot_40ms tp8_mns128_mbt8192 8 128 8192 lowest_anchor_infeasible False
9 tpot_40ms tp8_mns128_mbt16384 8 128 16384 lowest_anchor_infeasible False
10 tpot_120ms tp4_mns64_mbt8192 4 64 8192 0.025 0.2 unbracketed_requires_expansion True
11 tpot_120ms tp4_mns64_mbt16384 4 64 16384 0.025 0.2 unbracketed_requires_expansion True
12 tpot_120ms tp4_mns128_mbt8192 4 128 8192 0.025 0.2 unbracketed_requires_expansion True
13 tpot_120ms tp4_mns128_mbt16384 4 128 16384 0.025 0.2 unbracketed_requires_expansion True
14 tpot_120ms tp8_mns64_mbt8192 8 64 8192 0.0125 0.05 unbracketed_requires_expansion True
15 tpot_120ms tp8_mns64_mbt16384 8 64 16384 0.0125 0.05 unbracketed_requires_expansion True
16 tpot_120ms tp8_mns128_mbt8192 8 128 8192 0.0125 0.05 unbracketed_requires_expansion True
17 tpot_120ms tp8_mns128_mbt16384 8 128 16384 0.0125 0.05 unbracketed_requires_expansion True
18 tpot_150ms tp4_mns64_mbt8192 4 64 8192 0.6 0.4 adjacent_transition_bracketed False
19 tpot_150ms tp4_mns64_mbt16384 4 64 16384 0.6 0.4 adjacent_transition_bracketed False
20 tpot_150ms tp4_mns128_mbt8192 4 128 8192 0.6 0.4 adjacent_transition_bracketed False
21 tpot_150ms tp4_mns128_mbt16384 4 128 16384 0.6 0.4 adjacent_transition_bracketed False
22 tpot_150ms tp8_mns64_mbt8192 8 64 8192 0.3 0.15 adjacent_transition_bracketed False
23 tpot_150ms tp8_mns64_mbt16384 8 64 16384 0.2 0.15 adjacent_transition_bracketed False
24 tpot_150ms tp8_mns128_mbt8192 8 128 8192 0.2 0.15 adjacent_transition_bracketed False
25 tpot_150ms tp8_mns128_mbt16384 8 128 16384 0.3 0.15 adjacent_transition_bracketed False
26 tpot_180ms tp4_mns64_mbt8192 4 64 8192 0.8 0.6 upper_lattice_reached False
27 tpot_180ms tp4_mns64_mbt16384 4 64 16384 0.8 0.6 upper_lattice_reached False
28 tpot_180ms tp4_mns128_mbt8192 4 128 8192 0.8 0.6 upper_lattice_reached False
29 tpot_180ms tp4_mns128_mbt16384 4 128 16384 0.8 0.6 upper_lattice_reached False
30 tpot_180ms tp8_mns64_mbt8192 8 64 8192 0.4 0.2 upper_lattice_reached False
31 tpot_180ms tp8_mns64_mbt16384 8 64 16384 0.3 0.2 unbracketed_requires_expansion True
32 tpot_180ms tp8_mns128_mbt8192 8 128 8192 0.3 0.2 unbracketed_requires_expansion True
33 tpot_180ms tp8_mns128_mbt16384 8 128 16384 0.4 0.2 upper_lattice_reached False