KVCache simulator for LLM serving cluster routing research
Discrete-event simulator for evaluating KV cache-aware routing policies in prefill-disaggregated LLM serving clusters. Models a two-tier KV cache hierarchy (L0 GPU HBM + L1 CPU DRAM) with RDMA/PCIe link contention, architecture-derived roofline compute (MoE, MLA, DSA), and a cluster-wide meta-store for prefix-aware routing decisions. Includes 11 routing policies (random, round_robin, least_loaded, least_tokens, ttl_aware, precise, min_pd, cache_load, cache_score, estimated_ttft, prefix_affinity), HuggingFace config.json auto-parsing, built-in GPU hardware presets (H100/H800/H20/A100/B200), and ablation tooling for systematic policy comparison across real Alibaba serving traces. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
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configs/glm5-8xb200-blk512.yaml
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configs/glm5-8xb200-blk512.yaml
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# GLM-5 (zai-org/GLM-5) on 8 x B200 SXM (192GB each).
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# Architecture from HuggingFace config.json — all roofline coefficients
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# are derived automatically.
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model:
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name: glm-5
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# Core architecture (from HF config.json)
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num_layers: 78
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hidden_size: 6144
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num_attention_heads: 64
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num_kv_heads: 64 # formalism; MLA overrides KV cache sizing
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head_dim: 64
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intermediate_size: 12288 # shared expert FFN width
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dtype_bytes: 2 # BF16
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block_size_tokens: 512 # matches bailian-traces blksz_512
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# MoE: 256 routed + 1 shared, 8 active per token
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moe:
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num_experts: 256
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num_active_experts: 8
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num_shared_experts: 1
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expert_intermediate_size: 2048 # moe_intermediate_size
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# MLA (Multi-head Latent Attention): compressed KV cache
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mla:
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kv_lora_rank: 512
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q_lora_rank: 2048
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qk_nope_head_dim: 192
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qk_rope_head_dim: 64
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v_head_dim: 256
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# DSA (DeepSeek Sparse Attention): sub-quadratic past dense_window
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attention:
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type: dsa
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dense_window: 4096
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sparse_stride: 8
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first_dense_layers: 3
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hardware:
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# Aggregate of 8 x B200 in one tensor-parallel group.
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gpu_flops: 1.80e16 # 8 * 2.25 PFLOPS BF16 dense
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gpu_mem_bw: 6.40e13 # 8 * 8 TB/s HBM3e
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# KV budget after FP8 weights + activations. GLM-5 FP8 ~744GB of 1536GB.
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hbm_bytes: 500.0e9
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dram_bytes: 1.5e12 # ~1.5 TB usable CPU DRAM / v6d per node
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pcie_bw: 128.0e9 # PCIe Gen6 x16
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pcie_latency_us: 4.0
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rdma_bw: 50.0e9 # ConnectX-7 400 Gbps
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rdma_latency_us: 6.0
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max_batch_slots: 256
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prefill_chunk_tokens: 4096
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cluster:
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num_instances: 64
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meta_store:
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ttl_seconds: 300.0
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router:
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mode: min_pd
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precise_probe_latency_us: 50.0
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precise_probe_topk: 4
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load_alpha: 1.0
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sim:
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trace_path: bailian-traces/glm_coder_blksz_512_040915-040917.jsonl
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max_requests: null
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output_dir: runs/glm5_8xb200_blk512
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sample_interval_s: 1.0
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seed: 42
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