kernels/cuda: paged-attention kernel, dispatch, pinned host memory
CUDA layer for the paged-KV + swap work: - csrc: new paged_attention.cu plus updates across attention/gemm/norm/ activation/embedding/reduce kernels and common.cuh. - xserv-kernels: new dispatch module and kernel-binding updates. - xserv-cuda: cudaMallocHost/FreeHost bindings + PinnedBuffer (host swap pool backing) and offset-aware D2H/H2D copies used to move KV blocks between the GPU pool and pinned host memory. Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
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@@ -19,7 +19,9 @@ fn dispatch_unary(x: &Tensor, f32_fn: unsafe extern "C" fn(*const c_void, *mut c
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bf16_fn: unsafe extern "C" fn(*const c_void, *mut c_void, i32, *mut c_void)) -> Tensor {
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assert!(x.is_contiguous() && matches!(x.device(), Device::Cuda(_)));
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let out = Tensor::empty(x.shape(), x.dtype(), x.device());
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let n = x.numel() as i32;
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let n = x.numel();
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assert!(n <= i32::MAX as usize, "tensor too large for i32 kernel param ({n} elements)");
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let n = n as i32;
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unsafe {
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match x.dtype() {
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DType::F32 => f32_fn(x.data_ptr() as _, out.data_ptr() as *mut c_void, n, std::ptr::null_mut()),
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@@ -38,7 +40,9 @@ fn dispatch_binary(a: &Tensor, b: &Tensor,
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assert!(matches!(a.device(), Device::Cuda(_)));
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assert_eq!(a.dtype(), b.dtype());
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let out = Tensor::empty(a.shape(), a.dtype(), a.device());
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let n = a.numel() as i32;
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let n = a.numel();
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assert!(n <= i32::MAX as usize, "tensor too large for i32 kernel param ({n} elements)");
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let n = n as i32;
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unsafe {
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match a.dtype() {
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DType::F32 => f32_fn(a.data_ptr() as _, b.data_ptr() as _, out.data_ptr() as *mut c_void, n, std::ptr::null_mut()),
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@@ -55,7 +59,9 @@ pub fn silu(x: &Tensor) -> Tensor { dispatch_unary(x, launch_silu_f32, launch_si
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pub fn scale(x: &Tensor, scale_val: f32) -> Tensor {
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assert!(x.is_contiguous() && matches!(x.device(), Device::Cuda(_)));
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let out = Tensor::empty(x.shape(), x.dtype(), x.device());
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let n = x.numel() as i32;
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let n = x.numel();
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assert!(n <= i32::MAX as usize, "tensor too large for i32 kernel param ({n} elements)");
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let n = n as i32;
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unsafe {
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match x.dtype() {
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DType::F32 => launch_scale_f32(x.data_ptr() as _, out.data_ptr() as *mut c_void, scale_val, n, std::ptr::null_mut()),
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@@ -77,7 +83,9 @@ pub fn silu_mul(gate: &Tensor, up: &Tensor) -> Tensor {
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assert!(matches!(gate.device(), Device::Cuda(_)));
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assert_eq!(gate.dtype(), DType::BF16, "silu_mul requires BF16");
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let out = Tensor::empty(gate.shape(), gate.dtype(), gate.device());
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let n = gate.numel() as i32;
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let n = gate.numel();
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assert!(n <= i32::MAX as usize, "tensor too large for i32 kernel param ({n} elements)");
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let n = n as i32;
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unsafe {
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launch_silu_mul_bf16(
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gate.data_ptr() as *const c_void,
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