phase 15: decode attention kernel + fused silu_mul + fused add_rmsnorm
Three performance optimizations targeting decode throughput: 1. Decode Attention Kernel (csrc/attention/flash_attention.cu): - Specialized kernel for Q_len=1 (decode step) - 256 threads parallelize across KV sequence dimension - Online softmax with block-level warp-shuffle reduction - Replaces FA2 kernel which wasted 63/64 threads for decode - flash_attention() auto-dispatches when q_len==1 2. Fused SiLU×Mul (csrc/activation/activations.cu): - Single kernel: out = silu(gate) * up - Saves 1 HBM read + 1 HBM write per FFN layer (N elements) - Eliminates intermediate tensor allocation 3. Fused Add+RMSNorm (csrc/normalization/rmsnorm.cu): - Single kernel: (normed, sum) = (rmsnorm(x+residual), x+residual) - Saves 1 full HBM round-trip per attention block - Eliminates separate add + rmsnorm kernel pair Performance analysis: - At current short sequences (max 79 tokens), these optimizations provide marginal benefit because the bottleneck is cuBLAS GEMV overhead: 252 weight matrix reads × ~32MB each = 15.5 GB per decode step. Theoretical minimum at 1.79 TB/s = 8.7ms, actual ~78ms (9x gap). - The fused kernels and decode attention will show larger gains at longer sequences where attention and element-wise ops dominate. - Next optimization target: CUDA Graphs to eliminate kernel launch overhead, or custom GEMV kernels to replace cuBLAS for M=1. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
This commit is contained in:
@@ -45,6 +45,18 @@ __global__ void scale_bf16_kernel(const __nv_bfloat16* x, __nv_bfloat16* out, fl
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if (idx < n) out[idx] = __float2bfloat16(__bfloat162float(x[idx]) * scale);
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}
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// Fused SiLU×Mul: out = silu(gate) * up
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__global__ void silu_mul_bf16_kernel(const __nv_bfloat16* gate, const __nv_bfloat16* up,
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__nv_bfloat16* out, int n) {
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int idx = blockIdx.x * blockDim.x + threadIdx.x;
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if (idx < n) {
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float g = __bfloat162float(gate[idx]);
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float u = __bfloat162float(up[idx]);
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float silu_g = g / (1.0f + expf(-g));
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out[idx] = __float2bfloat16(silu_g * u);
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}
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}
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// Element-wise add: out = a + b
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__global__ void add_f32_kernel(const float* a, const float* b, float* out, int n) {
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int idx = blockIdx.x * blockDim.x + threadIdx.x;
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@@ -132,4 +144,11 @@ void launch_mul_bf16(const void* a, const void* b, void* out, int n, void* strea
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(const __nv_bfloat16*)a, (const __nv_bfloat16*)b, (__nv_bfloat16*)out, n);
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}
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void launch_silu_mul_bf16(const void* gate, const void* up, void* out, int n, void* stream) {
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int block = 256;
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int grid = (n + block - 1) / block;
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silu_mul_bf16_kernel<<<grid, block, 0, (cudaStream_t)stream>>>(
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(const __nv_bfloat16*)gate, (const __nv_bfloat16*)up, (__nv_bfloat16*)out, n);
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}
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}
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@@ -196,6 +196,177 @@ __global__ void flash_attention_bf16_kernel(
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}
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}
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// ============================================================
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// Decode Attention kernel: optimized for Q_len=1 (single-token decode).
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// Parallelizes across KV sequence dimension instead of Q rows.
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//
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// Grid: (batch * num_q_heads, 1) — one block per Q head
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// Block: 256 threads — each thread handles ceil(kv_len / 256) KV positions
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// Uses online softmax reduction across threads.
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// ============================================================
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#define DECODE_THREADS 256
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#define HEAD_DIM_MAX 128
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__global__ void decode_attention_bf16_kernel(
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const __nv_bfloat16* __restrict__ Q,
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const __nv_bfloat16* __restrict__ K,
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const __nv_bfloat16* __restrict__ V,
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__nv_bfloat16* __restrict__ O,
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int num_q_heads, int num_kv_heads,
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int kv_len, int head_dim,
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float scale
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) {
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int bh = blockIdx.x;
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int batch_idx = bh / num_q_heads;
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int q_head = bh % num_q_heads;
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// GQA mapping
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int heads_per_group = num_q_heads / num_kv_heads;
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int kv_head = q_head / heads_per_group;
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int tid = threadIdx.x;
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// Pointers to this batch/head's data
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// Q: [batch, num_q_heads, 1, head_dim]
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const __nv_bfloat16* Q_ptr = Q + ((long long)batch_idx * num_q_heads + q_head) * head_dim;
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// K/V: [batch, num_kv_heads, kv_len, head_dim]
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const __nv_bfloat16* K_base = K + ((long long)batch_idx * num_kv_heads + kv_head) * kv_len * head_dim;
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const __nv_bfloat16* V_base = V + ((long long)batch_idx * num_kv_heads + kv_head) * kv_len * head_dim;
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__nv_bfloat16* O_ptr = O + ((long long)batch_idx * num_q_heads + q_head) * head_dim;
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// Load Q vector into registers (head_dim <= 128)
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float q_reg[HEAD_DIM_MAX];
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for (int d = 0; d < head_dim; d++) {
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q_reg[d] = __bfloat162float(Q_ptr[d]);
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}
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// Each thread processes a chunk of KV positions
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// Thread tid handles positions: tid, tid+DECODE_THREADS, tid+2*DECODE_THREADS, ...
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float local_max = -INFINITY;
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float local_sum = 0.0f;
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float local_O[HEAD_DIM_MAX];
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for (int d = 0; d < head_dim; d++) {
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local_O[d] = 0.0f;
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}
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for (int pos = tid; pos < kv_len; pos += DECODE_THREADS) {
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// Compute dot(Q, K[pos]) * scale
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const __nv_bfloat16* K_pos = K_base + pos * head_dim;
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float dot = 0.0f;
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for (int d = 0; d < head_dim; d++) {
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dot += q_reg[d] * __bfloat162float(K_pos[d]);
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}
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float s = dot * scale;
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// Online softmax update
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float new_max = fmaxf(local_max, s);
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float correction = expf(local_max - new_max);
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float p = expf(s - new_max);
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// Rescale running sum and O
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local_sum = local_sum * correction + p;
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for (int d = 0; d < head_dim; d++) {
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local_O[d] = local_O[d] * correction;
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}
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// Accumulate V[pos] weighted by p
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const __nv_bfloat16* V_pos = V_base + pos * head_dim;
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for (int d = 0; d < head_dim; d++) {
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local_O[d] += p * __bfloat162float(V_pos[d]);
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}
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local_max = new_max;
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}
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// --- Block-level online softmax reduction ---
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// We need to combine (local_max, local_sum, local_O) across all threads.
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// Strategy: reduce max, then each thread rescales, then reduce sum and O.
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// Shared memory for reduction
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__shared__ float smem_max[32]; // one per warp
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__shared__ float smem_sum[32];
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__shared__ float smem_O[HEAD_DIM_MAX]; // final output accumulator
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// Step 1: Block-wide max reduction
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int lane = tid & 31;
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int warp_id = tid >> 5;
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int num_warps = DECODE_THREADS >> 5; // 8 warps
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float warp_max = local_max;
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#pragma unroll
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for (int offset = 16; offset > 0; offset >>= 1)
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warp_max = fmaxf(warp_max, __shfl_down_sync(0xffffffff, warp_max, offset));
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if (lane == 0) smem_max[warp_id] = warp_max;
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__syncthreads();
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float global_max;
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if (tid == 0) {
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global_max = smem_max[0];
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for (int i = 1; i < num_warps; i++)
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global_max = fmaxf(global_max, smem_max[i]);
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smem_max[0] = global_max;
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}
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__syncthreads();
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global_max = smem_max[0];
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// Step 2: Each thread rescales its local_sum and local_O with global_max
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float rescale = (local_max == -INFINITY) ? 0.0f : expf(local_max - global_max);
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local_sum *= rescale;
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for (int d = 0; d < head_dim; d++) {
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local_O[d] *= rescale;
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}
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// Step 3: Reduce sum across block
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float warp_sum = local_sum;
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#pragma unroll
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for (int offset = 16; offset > 0; offset >>= 1)
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warp_sum += __shfl_down_sync(0xffffffff, warp_sum, offset);
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if (lane == 0) smem_sum[warp_id] = warp_sum;
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__syncthreads();
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float global_sum;
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if (tid == 0) {
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global_sum = 0.0f;
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for (int i = 0; i < num_warps; i++)
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global_sum += smem_sum[i];
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smem_sum[0] = global_sum;
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}
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__syncthreads();
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global_sum = smem_sum[0];
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// Step 4: Reduce O across block (dimension by dimension using shared mem)
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float inv_sum = (global_sum > 0.0f) ? (1.0f / global_sum) : 0.0f;
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// Process head_dim in chunks: each iteration reduces one dimension
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// Use shared memory accumulator: each warp contributes via warp reduction + atomic
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// Actually simpler: iterate over dimensions, warp reduce each, then lane0 atomicAdd to smem_O
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// Initialize smem_O
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for (int d = tid; d < head_dim; d += DECODE_THREADS) {
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smem_O[d] = 0.0f;
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}
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__syncthreads();
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// Each thread adds its local_O contributions via warp reduction + atomicAdd
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for (int d = 0; d < head_dim; d++) {
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float val = local_O[d];
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// Warp-level reduction
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#pragma unroll
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for (int offset = 16; offset > 0; offset >>= 1)
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val += __shfl_down_sync(0xffffffff, val, offset);
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if (lane == 0) {
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atomicAdd(&smem_O[d], val);
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}
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}
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__syncthreads();
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// Thread 0..head_dim-1 write final output
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for (int d = tid; d < head_dim; d += DECODE_THREADS) {
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O_ptr[d] = __float2bfloat16(smem_O[d] * inv_sum);
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}
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}
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extern "C" {
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void launch_flash_attention_bf16(
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@@ -222,4 +393,24 @@ void launch_flash_attention_bf16(
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);
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}
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void launch_decode_attention_bf16(
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const void* Q, const void* K, const void* V, void* O,
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int batch, int num_q_heads, int num_kv_heads,
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int kv_len, int head_dim,
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float scale, int causal, void* stream
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) {
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int grid = batch * num_q_heads;
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int block = DECODE_THREADS;
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decode_attention_bf16_kernel<<<grid, block, 0, (cudaStream_t)stream>>>(
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(const __nv_bfloat16*)Q,
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(const __nv_bfloat16*)K,
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(const __nv_bfloat16*)V,
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(__nv_bfloat16*)O,
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num_q_heads, num_kv_heads,
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kv_len, head_dim,
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scale
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);
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}
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}
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@@ -63,6 +63,46 @@ __global__ void rmsnorm_bf16(
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}
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}
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// Fused Add + RMSNorm: sum_out = x + residual, normed_out = rmsnorm(sum_out, gamma, eps)
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// Each block handles one row of [hidden_size].
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__global__ void add_rmsnorm_bf16(
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const __nv_bfloat16* __restrict__ x,
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const __nv_bfloat16* __restrict__ residual,
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const __nv_bfloat16* __restrict__ gamma,
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__nv_bfloat16* __restrict__ normed_out,
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__nv_bfloat16* __restrict__ sum_out,
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int hidden_size, float eps
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) {
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int row = blockIdx.x;
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const __nv_bfloat16* x_row = x + row * hidden_size;
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const __nv_bfloat16* res_row = residual + row * hidden_size;
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__nv_bfloat16* sum_row = sum_out + row * hidden_size;
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__nv_bfloat16* norm_row = normed_out + row * hidden_size;
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// Pass 1: compute sum = x + residual, and accumulate sum_sq
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float sum_sq = 0.0f;
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for (int i = threadIdx.x; i < hidden_size; i += blockDim.x) {
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float s = __bfloat162float(x_row[i]) + __bfloat162float(res_row[i]);
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sum_row[i] = __float2bfloat16(s);
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sum_sq += s * s;
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}
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sum_sq = block_reduce_sum(sum_sq);
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__shared__ float s_rms_inv;
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if (threadIdx.x == 0) {
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s_rms_inv = rsqrtf(sum_sq / hidden_size + eps);
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}
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__syncthreads();
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// Pass 2: normed_out = sum * rms_inv * gamma
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float rms_inv = s_rms_inv;
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for (int i = threadIdx.x; i < hidden_size; i += blockDim.x) {
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float s = __bfloat162float(sum_row[i]);
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float g = __bfloat162float(gamma[i]);
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norm_row[i] = __float2bfloat16(s * rms_inv * g);
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}
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}
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extern "C" {
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void launch_rmsnorm_f32(const void* x, const void* gamma, void* out,
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@@ -80,4 +120,15 @@ void launch_rmsnorm_bf16(const void* x, const void* gamma, void* out,
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(__nv_bfloat16*)out, hidden_size, eps);
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}
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void launch_add_rmsnorm_bf16(const void* x, const void* residual, const void* gamma,
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void* normed_out, void* sum_out,
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int rows, int hidden_size, float eps, void* stream) {
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int block = (hidden_size < 1024) ? hidden_size : 1024;
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add_rmsnorm_bf16<<<rows, block, 0, (cudaStream_t)stream>>>(
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(const __nv_bfloat16*)x, (const __nv_bfloat16*)residual,
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(const __nv_bfloat16*)gamma,
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(__nv_bfloat16*)normed_out, (__nv_bfloat16*)sum_out,
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hidden_size, eps);
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}
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}
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