Gahow Wang
5f060902f6
Three CUDA bugs from the review after5b350ee/cfbd64dthat were missed by those commits: - flash_attention.cu decode_attention_bf16_kernel used atomicAdd to merge per-warp partials into smem_O — same nondeterminism pattern that5b350eealready fixed in paged_attention.cu and gemv.cu. This kernel is on the legacy forward_gpu_cache path plus the speculative bench baseline, so verify/decode parity depended on it. Replace with smem_O_warp[32][HEAD_DIM_MAX] partials reduced in fixed warp-id order. - causal_mask.cu computed the flat address as `batch_idx * rows * cols + row * cols + col` in int; batch=128 heads=28 seq=32768 already overflows int32. Promote the index to long long. - quantization/dequant_fp8.cu had `int total = num_experts * rows * cols` and `int expert_stride = rows * cols`; 32 experts × 8k × 8k overflows. Same fix pattern as the MoE dense kernels incfbd64d— 64-bit total / idx / expert_stride, and grid computed in long long.
54 lines
1.6 KiB
Plaintext
54 lines
1.6 KiB
Plaintext
#include <cuda_bf16.h>
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#include <cuda_fp8.h>
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#include "../common.cuh"
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// Dequantize FP8 E4M3 → BF16 with per-expert (per-batch-slice) FP32 scale.
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//
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// Input: src [num_experts, rows, cols] FP8 E4M3 (1 byte each)
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// scales [num_experts] FP32
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// Output: dst [num_experts, rows, cols] BF16
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//
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// Each element: dst[e, r, c] = bf16( float(src[e, r, c]) * scales[e] )
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__global__ void dequant_fp8e4m3_to_bf16_kernel(
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const __nv_fp8_e4m3* __restrict__ src,
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const float* __restrict__ scales,
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__nv_bfloat16* __restrict__ dst,
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int num_experts, int rows, int cols
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) {
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// 64-bit index: num_experts * rows * cols overflows int32 for 32 experts
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// at ~8k*8k weight matrices, same class as the MoE fix in cfbd64d.
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long long idx = (long long)blockIdx.x * blockDim.x + threadIdx.x;
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long long total = (long long)num_experts * rows * cols;
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if (idx >= total) return;
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long long expert_stride = (long long)rows * cols;
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int expert = (int)(idx / expert_stride);
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float scale = scales[expert];
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float val = float(src[idx]) * scale;
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dst[idx] = __float2bfloat16(val);
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}
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extern "C" {
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void launch_dequant_fp8e4m3_to_bf16(
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const void* src,
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const void* scales,
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void* dst,
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int num_experts, int rows, int cols,
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void* stream
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) {
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long long total = (long long)num_experts * rows * cols;
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int block = 256;
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int grid = (int)((total + block - 1) / block);
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dequant_fp8e4m3_to_bf16_kernel<<<grid, block, 0, (cudaStream_t)stream>>>(
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(const __nv_fp8_e4m3*)src,
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(const float*)scales,
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(__nv_bfloat16*)dst,
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num_experts, rows, cols
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);
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CUDA_CHECK_LAST_ERROR();
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}
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}
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