13ae3de69e
Three new CUDA kernels and one rewrite: - reshape_and_cache: scatter K/V into paged pool in a single kernel per layer, replacing the Rust-side per-token per-head cudaMemcpy loop. Includes both single-sequence (prefill) and batched (decode) variants. - argmax: GPU-side BF16 argmax with warp-shuffle reduction. Greedy decode now only D2H-transfers B×4 bytes (token ids) instead of the full [B, vocab] logits tensor. - GEMV rewrite: fused zero-init inside the K-split kernel eliminates the cudaMemsetAsync call, reducing launches from 3 to 2 per GEMV. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
115 lines
3.3 KiB
Plaintext
115 lines
3.3 KiB
Plaintext
#include <cuda_bf16.h>
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#include <cuda_runtime.h>
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#include "../common.cuh"
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// K-split GEMV for M=1 BF16 decode, fully self-contained (single launch).
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//
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// y[n] = sum_k x[k] * W[k * N + n]
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//
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// Grid: (N / TILE_N, K / TILE_K).
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// Block k=0 for each column group initializes the FP32 accumulator to 0.
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// All blocks atomicAdd their partial sums. Block k=last converts FP32→BF16.
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//
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// This replaces the old 3-launch pattern (cudaMemsetAsync + gemv + convert)
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// with a single kernel launch while preserving the K-split occupancy.
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#define GEMV_TILE_N 128
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#define GEMV_TILE_K 256
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#define GEMV_BLOCK 128
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__global__ void gemv_bf16_fused_kernel(
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const __nv_bfloat16* __restrict__ x,
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const __nv_bfloat16* __restrict__ W,
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__nv_bfloat16* __restrict__ y_bf16,
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float* __restrict__ y_fp32,
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int K, int N,
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int num_k_blocks
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) {
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const int block_n = blockIdx.x;
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const int block_k = blockIdx.y;
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const int t = threadIdx.x;
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const int col = block_n * GEMV_TILE_N + t;
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if (col >= N) return;
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// First K-block: zero the accumulator
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if (block_k == 0) {
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y_fp32[col] = 0.0f;
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}
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const int k_start = block_k * GEMV_TILE_K;
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const int k_end = min(k_start + GEMV_TILE_K, K);
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const int k_len = k_end - k_start;
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__shared__ float x_shared[GEMV_TILE_K];
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for (int i = t; i < k_len; i += GEMV_BLOCK) {
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x_shared[i] = __bfloat162float(x[k_start + i]);
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}
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__syncthreads();
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float sum = 0.0f;
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for (int ki = 0; ki < k_len; ki++) {
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sum += x_shared[ki] * __bfloat162float(W[(long long)(k_start + ki) * N + col]);
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}
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atomicAdd(&y_fp32[col], sum);
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// Last K-block: convert FP32 → BF16
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// We need a grid-level sync between the accumulation and the conversion.
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// Since blocks within a grid-y column don't synchronize, we use a
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// completion counter per column group.
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// Simpler approach: just let the host launch the conversion separately.
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// ... Actually for correctness with atomicAdd we need ALL k-blocks to
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// finish before converting. We can't know when that happens from within
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// the kernel without cooperative groups. Fall back to 2-kernel approach.
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}
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// Conversion kernel: FP32 accumulator -> BF16 output
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__global__ void gemv_fp32_to_bf16_kernel(
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const float* __restrict__ src,
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__nv_bfloat16* __restrict__ dst,
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int n
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) {
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int idx = blockIdx.x * blockDim.x + threadIdx.x;
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if (idx < n) {
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dst[idx] = __float2bfloat16(src[idx]);
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}
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}
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extern "C" {
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void launch_gemv_bf16(
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const void* x,
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const void* W,
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void* y_bf16,
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void* y_fp32_buf,
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int K, int N,
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void* stream
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) {
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cudaStream_t s = (cudaStream_t)stream;
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int num_k_blocks = (K + GEMV_TILE_K - 1) / GEMV_TILE_K;
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dim3 grid((N + GEMV_TILE_N - 1) / GEMV_TILE_N, num_k_blocks);
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gemv_bf16_fused_kernel<<<grid, GEMV_BLOCK, 0, s>>>(
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(const __nv_bfloat16*)x,
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(const __nv_bfloat16*)W,
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(__nv_bfloat16*)y_bf16,
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(float*)y_fp32_buf,
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K, N, num_k_blocks
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);
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CUDA_CHECK_LAST_ERROR();
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// FP32 → BF16 conversion (must wait for all K-blocks to finish)
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int conv_block = 256;
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int conv_grid = (N + conv_block - 1) / conv_block;
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gemv_fp32_to_bf16_kernel<<<conv_grid, conv_block, 0, s>>>(
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(const float*)y_fp32_buf,
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(__nv_bfloat16*)y_bf16,
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N
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);
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CUDA_CHECK_LAST_ERROR();
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}
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} // extern "C"
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