Gahow Wang
4c3f914459
CUDA layer for the paged-KV + swap work: - csrc: new paged_attention.cu plus updates across attention/gemm/norm/ activation/embedding/reduce kernels and common.cuh. - xserv-kernels: new dispatch module and kernel-binding updates. - xserv-cuda: cudaMallocHost/FreeHost bindings + PinnedBuffer (host swap pool backing) and offset-aware D2H/H2D copies used to move KV blocks between the GPU pool and pinned host memory. Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
56 lines
1.7 KiB
Plaintext
56 lines
1.7 KiB
Plaintext
#include <cuda_bf16.h>
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#include "../common.cuh"
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// Apply causal mask: set scores[row][col] = -inf where col > row + offset.
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// offset is used for KV cache: when query starts at position `offset`,
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// we allow attending to positions [0, offset + row].
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// scores: [batch, rows, cols] (flattened batch×heads)
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__global__ void causal_mask_f32(
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float* __restrict__ scores,
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int rows, int cols, int offset
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) {
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int batch_idx = blockIdx.z;
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int row = blockIdx.y;
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int col = blockIdx.x * blockDim.x + threadIdx.x;
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if (col < cols && col > row + offset) {
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scores[batch_idx * rows * cols + row * cols + col] = -INFINITY;
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}
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}
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__global__ void causal_mask_bf16(
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__nv_bfloat16* __restrict__ scores,
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int rows, int cols, int offset
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) {
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int batch_idx = blockIdx.z;
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int row = blockIdx.y;
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int col = blockIdx.x * blockDim.x + threadIdx.x;
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if (col < cols && col > row + offset) {
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scores[batch_idx * rows * cols + row * cols + col] = __float2bfloat16(-INFINITY);
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}
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}
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extern "C" {
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void launch_causal_mask_f32(void* scores, int batch, int rows, int cols,
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int offset, void* stream) {
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int block = 256;
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dim3 grid((cols + block - 1) / block, rows, batch);
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causal_mask_f32<<<grid, block, 0, (cudaStream_t)stream>>>(
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(float*)scores, rows, cols, offset);
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CUDA_CHECK_LAST_ERROR();
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}
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void launch_causal_mask_bf16(void* scores, int batch, int rows, int cols,
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int offset, void* stream) {
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int block = 256;
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dim3 grid((cols + block - 1) / block, rows, batch);
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causal_mask_bf16<<<grid, block, 0, (cudaStream_t)stream>>>(
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(__nv_bfloat16*)scores, rows, cols, offset);
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CUDA_CHECK_LAST_ERROR();
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}
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}
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