Gahow Wang
a842e432b5
Default-stream kernels run in order and every host read goes through a stream-ordered cudaMemcpy (to_device), so the per-op cudaDeviceSynchronize after each kernel was pure overhead — remove all 21 in tensor.rs. Host data is still correctly ordered by the D2H memcpy that reads it. Also zero op-output buffers with cudaMemset (device-side, async) instead of a blocking H2D memcpy of a host zero buffer on every allocation — that copy was itself a hidden per-op sync point. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
276 lines
7.7 KiB
Rust
276 lines
7.7 KiB
Rust
use std::ffi::c_void;
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use std::os::raw::c_char;
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pub type CudaStream = *mut c_void;
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pub const CUDA_MEMCPY_H2D: i32 = 1;
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pub const CUDA_MEMCPY_D2H: i32 = 2;
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pub const CUDA_SUCCESS: i32 = 0;
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pub const CUDA_ERROR_OUT_OF_MEMORY: i32 = 2;
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unsafe extern "C" {
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// --- Device ---
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pub fn cudaGetDeviceCount(count: *mut i32) -> i32;
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pub fn cudaSetDevice(device: i32) -> i32;
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pub fn cudaDeviceSynchronize() -> i32;
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// --- Memory ---
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pub fn cudaMalloc(devptr: *mut *mut u8, size: usize) -> i32;
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pub fn cudaFree(devptr: *mut u8) -> i32;
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pub fn cudaMemcpy(dst: *mut u8, src: *const u8, count: usize, kind: i32) -> i32;
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pub fn cudaMemset(devptr: *mut u8, value: i32, count: usize) -> i32;
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// --- Error ---
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pub fn cudaGetErrorString(error: i32) -> *const c_char;
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}
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// GPU kernels compiled from csrc/ by build.rs. Only linked when CUDA is
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// actually compiled (i.e. nvcc was present).
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#[cfg(not(no_cuda))]
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unsafe extern "C" {
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// Vector-add smoke test (csrc/test/vecadd.cu).
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pub fn launch_vecadd_f32(a: *const f32, b: *const f32, c: *mut f32, n: i32, stream: CudaStream);
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// Elementwise scale: out[i] = in[i] * alpha (csrc/ops/elementwise.cu).
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pub fn launch_scale_f32(
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input: *const f32,
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out: *mut f32,
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alpha: f32,
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n: i32,
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stream: CudaStream,
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);
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// Tiled GEMM: C = A @ B, row-major F32. A:[M,K] B:[K,N] C:[M,N]
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// (csrc/ops/gemm.cu).
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pub fn launch_gemm_tiled_f32(
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a: *const f32,
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b: *const f32,
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c: *mut f32,
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m: i32,
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n: i32,
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k: i32,
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stream: CudaStream,
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);
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// Out-of-place 2D transpose: out[j,i] = in[i,j]. in:[rows,cols] row-major,
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// out:[cols,rows] row-major (csrc/ops/gemm.cu).
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pub fn launch_transpose_f32(
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input: *const f32,
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out: *mut f32,
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rows: i32,
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cols: i32,
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stream: CudaStream,
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);
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}
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// Transformer / autograd op kernels (csrc/ops/nn.cu). Forward + backward for the
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// ops the Phase T4 tape engine needs. All F32, row-major, contiguous.
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#[cfg(not(no_cuda))]
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unsafe extern "C" {
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// Elementwise: out = a + b ; out = a * b.
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pub fn launch_add_f32(a: *const f32, b: *const f32, out: *mut f32, n: i32, s: CudaStream);
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pub fn launch_mul_f32(a: *const f32, b: *const f32, out: *mut f32, n: i32, s: CudaStream);
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// Broadcast bias add: out[r,c] = x[r,c] + bias[c]. x:[rows,cols], bias:[cols].
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pub fn launch_add_bias_f32(
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x: *const f32,
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bias: *const f32,
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out: *mut f32,
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rows: i32,
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cols: i32,
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s: CudaStream,
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);
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// Column-sum (over rows): dbias[c] = sum_r dout[r,c]. Bias backward.
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pub fn launch_sum_rows_f32(
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dout: *const f32,
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dbias: *mut f32,
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rows: i32,
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cols: i32,
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s: CudaStream,
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);
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// RMSNorm forward: writes y[rows,cols] and inv_rms[rows] (cached for bwd).
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pub fn launch_rms_norm_f32(
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x: *const f32,
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gamma: *const f32,
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y: *mut f32,
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inv_rms: *mut f32,
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rows: i32,
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cols: i32,
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eps: f32,
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s: CudaStream,
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);
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pub fn launch_rms_norm_dx_f32(
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x: *const f32,
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gamma: *const f32,
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dy: *const f32,
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inv_rms: *const f32,
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dx: *mut f32,
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rows: i32,
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cols: i32,
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s: CudaStream,
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);
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pub fn launch_rms_norm_dgamma_f32(
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x: *const f32,
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dy: *const f32,
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inv_rms: *const f32,
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dgamma: *mut f32,
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rows: i32,
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cols: i32,
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s: CudaStream,
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);
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// SiLU: y = x*sigmoid(x); backward dx.
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pub fn launch_silu_f32(x: *const f32, y: *mut f32, n: i32, s: CudaStream);
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pub fn launch_silu_dx_f32(x: *const f32, dy: *const f32, dx: *mut f32, n: i32, s: CudaStream);
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// RoPE (rotate_half), x:[tokens,heads,head_dim], position = token index.
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pub fn launch_rope_f32(
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x: *const f32,
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y: *mut f32,
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tokens: i32,
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heads: i32,
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head_dim: i32,
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theta: f32,
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s: CudaStream,
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);
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pub fn launch_rope_dx_f32(
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dy: *const f32,
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dx: *mut f32,
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tokens: i32,
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heads: i32,
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head_dim: i32,
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theta: f32,
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s: CudaStream,
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);
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// Row-wise softmax + Jacobian backward.
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pub fn launch_softmax_f32(x: *const f32, y: *mut f32, rows: i32, cols: i32, s: CudaStream);
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pub fn launch_softmax_dx_f32(
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y: *const f32,
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dy: *const f32,
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dx: *mut f32,
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rows: i32,
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cols: i32,
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s: CudaStream,
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);
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// Cross-entropy: fwd writes probs[rows,cols] + per-row loss[rows];
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// bwd dx = scale*(probs - onehot).
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pub fn launch_cross_entropy_fwd_f32(
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x: *const f32,
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target: *const i32,
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probs: *mut f32,
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loss: *mut f32,
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rows: i32,
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cols: i32,
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s: CudaStream,
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);
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pub fn launch_cross_entropy_dx_f32(
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probs: *const f32,
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target: *const i32,
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dx: *mut f32,
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rows: i32,
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cols: i32,
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scale: f32,
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s: CudaStream,
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);
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}
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// Structural ops for the tiny transformer (csrc/ops/model.cu): token embedding
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// (gather fwd / scatter-add bwd) and a 3D axis-(0,1) transpose for the multi-head
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// attention layout. F32 values, I32 ids, row-major contiguous.
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#[cfg(not(no_cuda))]
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unsafe extern "C" {
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// Embedding: out[s,:] = table[ids[s], :]. table:[vocab,dim], ids:[seq] (I32).
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pub fn launch_embedding_fwd_f32(
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table: *const f32,
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ids: *const i32,
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out: *mut f32,
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seq: i32,
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dim: i32,
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s: CudaStream,
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);
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// Scatter-add: dtable[ids[s],:] += dout[s,:] (dtable pre-zeroed; atomic).
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pub fn launch_embedding_bwd_f32(
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dout: *const f32,
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ids: *const i32,
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dtable: *mut f32,
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seq: i32,
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dim: i32,
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s: CudaStream,
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);
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// 3D axis-(0,1) transpose: in:[a,b,c] -> out:[b,a,c]. out[j,i,k]=in[i,j,k].
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pub fn launch_transpose_3d01_f32(
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input: *const f32,
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out: *mut f32,
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a: i32,
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b: i32,
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c: i32,
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s: CudaStream,
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);
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}
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// GPU-side optimizer kernels (csrc/ops/optim.cu): AdamW step (m/v on device) and
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// the global grad-norm reduction + in-place rescale (Phase T7).
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#[cfg(not(no_cuda))]
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unsafe extern "C" {
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// One in-place AdamW step over a parameter tensor of `n` elements. `bc1`/`bc2`
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// are the bias-correction denominators 1-beta^t.
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#[allow(clippy::too_many_arguments)]
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pub fn launch_adamw_step_f32(
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p: *mut f32,
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g: *const f32,
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m: *mut f32,
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v: *mut f32,
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lr: f32,
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b1: f32,
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b2: f32,
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eps: f32,
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wd: f32,
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bc1: f32,
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bc2: f32,
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n: i32,
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s: CudaStream,
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);
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// acc += sum_i g[i]^2 (acc is one f32 on device, pre-zeroed). atomicAdd.
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pub fn launch_sumsq_accum_f32(g: *const f32, acc: *mut f32, n: i32, s: CudaStream);
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// In-place scalar scale: x[i] *= factor.
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pub fn launch_scale_inplace_f32(x: *mut f32, factor: f32, n: i32, s: CudaStream);
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}
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// cuBLAS — the production GEMM backend (Phase T7) and the correctness oracle the
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// T3 GEMM tests still compare against. Declared (and linked, see build.rs) only
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// when CUDA is compiled in.
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#[cfg(not(no_cuda))]
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pub type CublasHandle = *mut c_void;
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#[cfg(not(no_cuda))]
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unsafe extern "C" {
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pub fn cublasCreate_v2(handle: *mut CublasHandle) -> i32;
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pub fn cublasDestroy_v2(handle: CublasHandle) -> i32;
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pub fn cublasSgemm_v2(
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handle: CublasHandle,
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transa: i32,
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transb: i32,
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m: i32,
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n: i32,
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k: i32,
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alpha: *const f32,
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a: *const f32,
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lda: i32,
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b: *const f32,
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ldb: i32,
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beta: *const f32,
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c: *mut f32,
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ldc: i32,
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) -> i32;
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}
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#[cfg(not(no_cuda))]
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pub const CUBLAS_OP_N: i32 = 0;
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#[cfg(not(no_cuda))]
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pub const CUBLAS_OP_T: i32 = 1;
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