Gahow Wang
7fb1a29057
Phase T5 structural ops on top of the T4 set, needed to assemble the tiny transformer: - embedding: gather rows by I32 ids (CUDA kernel) / scatter-add backward (atomic, so repeated ids accumulate). csrc/ops/model.cu + ffi. - reshape: contiguous metadata-only view (Tensor::reshape), no kernel. - transpose_3d01: [a,b,c]->[b,a,c] for the multi-head layout (kernel). - autograd nodes: embedding/reshape/transpose_3d01/transpose_2d, plus split_heads (->Vec<Var>) / merge_heads for per-head attention. - tape: Var::zero_grad + set_value so a hand-written GD step can update params and clear grads between steps. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
67 lines
3.1 KiB
Plaintext
67 lines
3.1 KiB
Plaintext
// Structural ops the tiny transformer (Phase T5) needs on top of the T4 op set:
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// token embedding (gather forward / scatter-add backward) and a 3D axis-(0,1)
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// transpose used to lay out multi-head attention ([seq,heads,hd] <-> [heads,seq,hd]).
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//
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// reshape is a pure metadata change (no data movement) and so has no kernel — it
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// lives entirely in the Rust Tensor layer. All kernels here are F32 row-major
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// contiguous; ids are I32. Each launcher matches the existing csrc/ style.
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extern "C" {
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// =====================================================================
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// Embedding: gather rows of a table by integer ids.
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// table:[vocab, dim], ids:[seq] (I32) -> out[s,:] = table[ids[s], :]
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// Backward (scatter-add): dtable[ids[s], :] += dout[s, :]. Multiple positions
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// may map to the same id, so the accumulation must be atomic.
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// =====================================================================
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__global__ void embedding_fwd_k(const float* table, const int* ids, float* out,
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int seq, int dim) {
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int i = blockIdx.x * blockDim.x + threadIdx.x; // over seq*dim
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if (i >= seq * dim) return;
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int s = i / dim, c = i % dim;
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out[i] = table[ids[s] * dim + c];
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}
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void launch_embedding_fwd_f32(const float* table, const int* ids, float* out,
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int seq, int dim, void* s) {
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int n = seq * dim, blk = 256, grid = (n + blk - 1) / blk;
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embedding_fwd_k<<<grid, blk, 0, (cudaStream_t)s>>>(table, ids, out, seq, dim);
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}
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// dtable is assumed pre-zeroed (Tensor::zeros). Scatter-add with atomics so
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// repeated ids accumulate correctly.
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__global__ void embedding_bwd_k(const float* dout, const int* ids, float* dtable,
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int seq, int dim) {
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int i = blockIdx.x * blockDim.x + threadIdx.x; // over seq*dim
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if (i >= seq * dim) return;
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int s = i / dim, c = i % dim;
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atomicAdd(&dtable[ids[s] * dim + c], dout[i]);
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}
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void launch_embedding_bwd_f32(const float* dout, const int* ids, float* dtable,
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int seq, int dim, void* s) {
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int n = seq * dim, blk = 256, grid = (n + blk - 1) / blk;
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embedding_bwd_k<<<grid, blk, 0, (cudaStream_t)s>>>(dout, ids, dtable, seq, dim);
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}
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// =====================================================================
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// 3D axis-(0,1) transpose: in:[a,b,c] -> out:[b,a,c] (last dim contiguous).
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// out[j, i, k] = in[i, j, k]
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// Its own backward is the same op with (a,b) swapped, so one kernel suffices.
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// =====================================================================
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__global__ void transpose_3d01_k(const float* in, float* out, int a, int b, int c) {
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int idx = blockIdx.x * blockDim.x + threadIdx.x; // over a*b*c
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if (idx >= a * b * c) return;
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int k = idx % c;
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int j = (idx / c) % b;
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int i = idx / (b * c);
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// out index: ((j*a) + i)*c + k
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out[(j * a + i) * c + k] = in[idx];
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}
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void launch_transpose_3d01_f32(const float* in, float* out, int a, int b, int c, void* s) {
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int n = a * b * c, blk = 256, grid = (n + blk - 1) / blk;
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transpose_3d01_k<<<grid, blk, 0, (cudaStream_t)s>>>(in, out, a, b, c);
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}
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} // extern "C"
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