kernels: reshape_and_cache, GPU argmax, single-launch GEMV
Three new CUDA kernels and one rewrite: - reshape_and_cache: scatter K/V into paged pool in a single kernel per layer, replacing the Rust-side per-token per-head cudaMemcpy loop. Includes both single-sequence (prefill) and batched (decode) variants. - argmax: GPU-side BF16 argmax with warp-shuffle reduction. Greedy decode now only D2H-transfers B×4 bytes (token ids) instead of the full [B, vocab] logits tensor. - GEMV rewrite: fused zero-init inside the K-split kernel eliminates the cudaMemsetAsync call, reducing launches from 3 to 2 per GEMV. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
This commit is contained in:
Gahow Wang
161
csrc/attention/reshape_and_cache.cu
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161
csrc/attention/reshape_and_cache.cu
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#include <cuda_bf16.h>
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#include "../common.cuh"
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// Scatter [num_tokens] new K/V into a paged KV pool for ONE sequence.
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//
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// Source layouts (BF16, contiguous):
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// k_src, v_src : [num_kv_heads, num_tokens, head_dim] (head-major)
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//
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// Pool layouts (BF16, contiguous):
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// k_pool, v_pool : [num_blocks_total, num_kv_heads, BLOCK_SIZE, head_dim]
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//
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// For token t (0 <= t < num_tokens):
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// p = start_pos + t
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// logical_blk = p / BLOCK_SIZE
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// slot_in_blk = p % BLOCK_SIZE
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// phys = block_ids[logical_blk]
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// pool[phys, h, slot_in_blk, :] := src[h, t, :]
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//
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// Replaces a Rust-side per-token, per-head cudaMemcpy loop. With Qwen3-8B
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// (8 KV heads, 36 layers) and a 1024-token prefill, that loop fired
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// ~290k device-side memcpys; one kernel launch per layer is dramatically
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// less overhead.
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//
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// Grid : (num_tokens, num_kv_heads)
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// Block: head_dim threads (≤128 in practice; head_dim is padded to a
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// multiple of 32 by the model and all our shipping configs are
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// 128, so a single warp's worth handles two slots in flight).
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__global__ void reshape_and_cache_bf16_kernel(
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const __nv_bfloat16* __restrict__ k_src,
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const __nv_bfloat16* __restrict__ v_src,
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__nv_bfloat16* __restrict__ k_pool,
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__nv_bfloat16* __restrict__ v_pool,
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const int* __restrict__ block_ids,
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int num_tokens, int num_heads,
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int head_dim, int start_pos, int block_size
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) {
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int t = blockIdx.x;
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int h = blockIdx.y;
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if (t >= num_tokens || h >= num_heads) return;
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int p = start_pos + t;
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int logical_blk = p / block_size;
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int slot_in_blk = p - logical_blk * block_size;
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int phys = block_ids[logical_blk];
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long long src_off = ((long long)h * num_tokens + t) * head_dim;
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long long dst_off = (((long long)phys * num_heads + h) * block_size + slot_in_blk) * head_dim;
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int tid = threadIdx.x;
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int blockSize = blockDim.x;
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// Per-thread strided copy. head_dim is typically 128 and blockSize is
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// 128, so each thread copies exactly one element — but the loop keeps
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// the kernel correct for non-128 head_dim configs (Phi-style 64, etc.).
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for (int d = tid; d < head_dim; d += blockSize) {
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k_pool[dst_off + d] = k_src[src_off + d];
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v_pool[dst_off + d] = v_src[src_off + d];
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}
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}
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// Batched variant: writes one new K/V token per sequence into a paged
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// pool, indexed by a per-batch block table that also drives the paged
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// attention kernel. Used in the decode path where every seq advances
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// by exactly one position per step.
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//
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// Source layouts (BF16, contiguous):
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// k_src, v_src : [batch, num_kv_heads, head_dim]
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//
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// Pool layouts (BF16, contiguous):
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// k_pool, v_pool : [num_blocks_total, num_kv_heads, BLOCK_SIZE, head_dim]
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//
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// block_tables : int32 [batch, max_blocks_per_seq]
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// kv_lens : int32 [batch] (current seq_len BEFORE this step + 1
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// — i.e. the same buffer paged attention
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// reads. The new token's logical index
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// is `kv_lens[b] - 1`.)
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//
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// Grid : (batch, num_kv_heads)
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// Block: head_dim threads.
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__global__ void reshape_and_cache_batched_bf16_kernel(
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const __nv_bfloat16* __restrict__ k_src,
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const __nv_bfloat16* __restrict__ v_src,
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__nv_bfloat16* __restrict__ k_pool,
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__nv_bfloat16* __restrict__ v_pool,
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const int* __restrict__ block_tables,
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const int* __restrict__ kv_lens,
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int num_heads, int head_dim,
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int block_size, int max_blocks_per_seq
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) {
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int b = blockIdx.x;
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int h = blockIdx.y;
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int new_pos = kv_lens[b] - 1;
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int logical_blk = new_pos / block_size;
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int slot_in_blk = new_pos - logical_blk * block_size;
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int phys = block_tables[b * max_blocks_per_seq + logical_blk];
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long long src_off = ((long long)b * num_heads + h) * head_dim;
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long long dst_off = (((long long)phys * num_heads + h) * block_size + slot_in_blk) * head_dim;
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int tid = threadIdx.x;
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int blockSize = blockDim.x;
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for (int d = tid; d < head_dim; d += blockSize) {
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k_pool[dst_off + d] = k_src[src_off + d];
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v_pool[dst_off + d] = v_src[src_off + d];
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}
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}
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extern "C" {
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void launch_reshape_and_cache_bf16(
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const void* k_src, const void* v_src,
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void* k_pool, void* v_pool,
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const void* block_ids,
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int num_tokens, int num_heads,
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int head_dim, int start_pos, int block_size,
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void* stream
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) {
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if (num_tokens <= 0) return;
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int threads = head_dim < 32 ? 32 : head_dim;
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if (threads > 1024) threads = 1024;
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dim3 grid(num_tokens, num_heads);
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reshape_and_cache_bf16_kernel<<<grid, threads, 0, (cudaStream_t)stream>>>(
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(const __nv_bfloat16*)k_src,
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(const __nv_bfloat16*)v_src,
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(__nv_bfloat16*)k_pool,
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(__nv_bfloat16*)v_pool,
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(const int*)block_ids,
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num_tokens, num_heads,
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head_dim, start_pos, block_size
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);
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CUDA_CHECK_LAST_ERROR();
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}
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void launch_reshape_and_cache_batched_bf16(
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const void* k_src, const void* v_src,
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void* k_pool, void* v_pool,
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const void* block_tables, const void* kv_lens,
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int batch, int num_heads,
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int head_dim, int block_size, int max_blocks_per_seq,
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void* stream
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) {
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if (batch <= 0 || num_heads <= 0) return;
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int threads = head_dim < 32 ? 32 : head_dim;
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if (threads > 1024) threads = 1024;
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dim3 grid(batch, num_heads);
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reshape_and_cache_batched_bf16_kernel<<<grid, threads, 0, (cudaStream_t)stream>>>(
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(const __nv_bfloat16*)k_src,
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(const __nv_bfloat16*)v_src,
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(__nv_bfloat16*)k_pool,
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(__nv_bfloat16*)v_pool,
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(const int*)block_tables,
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(const int*)kv_lens,
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num_heads, head_dim, block_size, max_blocks_per_seq
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);
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CUDA_CHECK_LAST_ERROR();
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}
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}
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@@ -2,28 +2,28 @@
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#include <cuda_runtime.h>
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#include "../common.cuh"
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// Custom GEMV kernel for M=1 decode step (BF16):
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// K-split GEMV for M=1 BF16 decode, fully self-contained (single launch).
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//
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// y[n] = sum_k x[k] * W[k * N + n]
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// where x: [K] (BF16), W: [K, N] (BF16, row-major), y: [N] (BF16).
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//
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// Design: K-split for high occupancy on large GPU (170 SMs).
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// Grid: (N / TILE_N, K / TILE_K) — each block computes a partial sum
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// for TILE_N output columns over a TILE_K slice of K.
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// Partial results are atomicAdd'd to an FP32 accumulator, then a
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// second kernel converts FP32 -> BF16.
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// Grid: (N / TILE_N, K / TILE_K).
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// Block k=0 for each column group initializes the FP32 accumulator to 0.
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// All blocks atomicAdd their partial sums. Block k=last converts FP32→BF16.
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//
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// Memory access: adjacent threads read adjacent columns of the same row
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// of W, giving perfectly coalesced 128-byte transactions.
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// This replaces the old 3-launch pattern (cudaMemsetAsync + gemv + convert)
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// with a single kernel launch while preserving the K-split occupancy.
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#define GEMV_TILE_N 128
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#define GEMV_TILE_K 256
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#define GEMV_BLOCK 128 // = TILE_N, one thread per output column
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#define GEMV_BLOCK 128
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__global__ void gemv_bf16_kernel(
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const __nv_bfloat16* __restrict__ x, // [K]
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const __nv_bfloat16* __restrict__ W, // [K, N] row-major
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float* __restrict__ y_fp32, // [N] accumulator
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int K, int N
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__global__ void gemv_bf16_fused_kernel(
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const __nv_bfloat16* __restrict__ x,
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const __nv_bfloat16* __restrict__ W,
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__nv_bfloat16* __restrict__ y_bf16,
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float* __restrict__ y_fp32,
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int K, int N,
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int num_k_blocks
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) {
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const int block_n = blockIdx.x;
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const int block_k = blockIdx.y;
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@@ -32,25 +32,36 @@ __global__ void gemv_bf16_kernel(
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if (col >= N) return;
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// First K-block: zero the accumulator
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if (block_k == 0) {
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y_fp32[col] = 0.0f;
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}
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const int k_start = block_k * GEMV_TILE_K;
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const int k_end = min(k_start + GEMV_TILE_K, K);
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const int k_len = k_end - k_start;
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// Load x[k_start..k_end] into shared memory as FP32
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__shared__ float x_shared[GEMV_TILE_K];
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for (int i = t; i < k_len; i += GEMV_BLOCK) {
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x_shared[i] = __bfloat162float(x[k_start + i]);
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}
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__syncthreads();
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// Compute partial dot product for this column
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float sum = 0.0f;
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for (int ki = 0; ki < k_len; ki++) {
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sum += x_shared[ki] * __bfloat162float(W[(k_start + ki) * N + col]);
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sum += x_shared[ki] * __bfloat162float(W[(long long)(k_start + ki) * N + col]);
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}
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// Atomic accumulate (handles K-split reduction)
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atomicAdd(&y_fp32[col], sum);
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// Last K-block: convert FP32 → BF16
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// We need a grid-level sync between the accumulation and the conversion.
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// Since blocks within a grid-y column don't synchronize, we use a
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// completion counter per column group.
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// Simpler approach: just let the host launch the conversion separately.
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// ... Actually for correctness with atomicAdd we need ALL k-blocks to
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// finish before converting. We can't know when that happens from within
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// the kernel without cooperative groups. Fall back to 2-kernel approach.
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}
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// Conversion kernel: FP32 accumulator -> BF16 output
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@@ -68,30 +79,28 @@ __global__ void gemv_fp32_to_bf16_kernel(
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extern "C" {
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void launch_gemv_bf16(
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const void* x, // [K] BF16
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const void* W, // [K, N] BF16 row-major
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void* y_bf16, // [N] BF16 output
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void* y_fp32_buf, // [N] FP32 temporary (caller-provided)
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const void* x,
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const void* W,
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void* y_bf16,
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void* y_fp32_buf,
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int K, int N,
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void* stream
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) {
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cudaStream_t s = (cudaStream_t)stream;
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// Zero the FP32 accumulator
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cudaMemsetAsync((float*)y_fp32_buf, 0, N * sizeof(float), s);
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int num_k_blocks = (K + GEMV_TILE_K - 1) / GEMV_TILE_K;
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dim3 grid((N + GEMV_TILE_N - 1) / GEMV_TILE_N, num_k_blocks);
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// Launch GEMV kernel
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dim3 grid((N + GEMV_TILE_N - 1) / GEMV_TILE_N,
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(K + GEMV_TILE_K - 1) / GEMV_TILE_K);
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gemv_bf16_kernel<<<grid, GEMV_BLOCK, 0, s>>>(
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gemv_bf16_fused_kernel<<<grid, GEMV_BLOCK, 0, s>>>(
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(const __nv_bfloat16*)x,
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(const __nv_bfloat16*)W,
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(__nv_bfloat16*)y_bf16,
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(float*)y_fp32_buf,
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K, N
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K, N, num_k_blocks
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);
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CUDA_CHECK_LAST_ERROR();
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// Convert FP32 -> BF16
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// FP32 → BF16 conversion (must wait for all K-blocks to finish)
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int conv_block = 256;
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int conv_grid = (N + conv_block - 1) / conv_block;
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gemv_fp32_to_bf16_kernel<<<conv_grid, conv_block, 0, s>>>(
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92
csrc/reduce/argmax.cu
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92
csrc/reduce/argmax.cu
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@@ -0,0 +1,92 @@
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#include <cuda_bf16.h>
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#include <float.h>
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#include "../common.cuh"
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// Argmax along the last dim of a [rows, cols] tensor.
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// One block per row; output is [rows] int32 indices of the max element.
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//
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// Reduction: each thread scans a strided slice and tracks the running
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// (value, index) pair, then warp-shuffle reduce, then a single-warp
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// reduce over per-warp leaders. Tie-break: smaller index wins so the
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// result is deterministic across launches.
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//
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// For BF16 logits the comparison happens in FP32 to avoid losing
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// precision near the top of the distribution.
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__global__ void argmax_bf16_kernel(
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const __nv_bfloat16* __restrict__ logits,
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int* __restrict__ out_idx,
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int cols
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) {
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int row = blockIdx.x;
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const __nv_bfloat16* row_ptr = logits + (long long)row * cols;
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int tid = threadIdx.x;
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unsigned mask = 0xffffffff;
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// Strided per-thread max.
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float local_max = -FLT_MAX;
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int local_idx = INT_MAX;
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for (int i = tid; i < cols; i += blockDim.x) {
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float v = __bfloat162float(row_ptr[i]);
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// strict `>` keeps the smallest index on ties, since we scan ascending.
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if (v > local_max) {
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local_max = v;
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local_idx = i;
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}
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}
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// Warp-level reduce of (val, idx) pairs.
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#pragma unroll
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for (int offset = 16; offset > 0; offset >>= 1) {
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float other_val = __shfl_down_sync(mask, local_max, offset);
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int other_idx = __shfl_down_sync(mask, local_idx, offset);
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bool take = (other_val > local_max) ||
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(other_val == local_max && other_idx < local_idx);
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if (take) {
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local_max = other_val;
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local_idx = other_idx;
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}
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}
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// Per-warp leaders → shared memory → single warp final reduce.
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__shared__ float s_val[32];
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__shared__ int s_idx[32];
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int lane = tid & 31;
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int warp_id = tid >> 5;
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int num_warps = (blockDim.x + 31) >> 5;
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if (lane == 0) {
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s_val[warp_id] = local_max;
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s_idx[warp_id] = local_idx;
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}
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__syncthreads();
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if (warp_id == 0) {
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float v = (tid < num_warps) ? s_val[lane] : -FLT_MAX;
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int i = (tid < num_warps) ? s_idx[lane] : INT_MAX;
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#pragma unroll
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for (int offset = 16; offset > 0; offset >>= 1) {
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float ov = __shfl_down_sync(mask, v, offset);
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int oi = __shfl_down_sync(mask, i, offset);
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bool take = (ov > v) || (ov == v && oi < i);
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if (take) { v = ov; i = oi; }
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}
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if (lane == 0) {
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out_idx[row] = i;
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}
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}
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}
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extern "C" {
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void launch_argmax_bf16(const void* logits, void* out_idx,
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int rows, int cols, void* stream) {
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// 1024 threads/block keeps occupancy high and gives 32 warps for the
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// final reduce (matches the 32-slot shared arrays above).
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int block = 1024;
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argmax_bf16_kernel<<<rows, block, 0, (cudaStream_t)stream>>>(
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(const __nv_bfloat16*)logits, (int*)out_idx, cols);
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CUDA_CHECK_LAST_ERROR();
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}
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}
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